library ieee;

use ieee.std_logic_1164.all;
use std.textio.all;
use work.all;

entity p21tb is
end p21tb;

architecture behav of p21tb is
		signal op_t: bit;
		signal status_t: bit;
		signal ain_t: bit_vector(3 downto 0);
		signal bin_t: bit_vector(3 downto 0);
		signal reg2_t: bit_vector(3 downto 0);
		signal clk_t: bit;
		signal start_t: bit;
		signal play: bit;
		

	
	component prob21
	port(misccontrol: in bit;
		status: out bit;
		clk: out bit;
		ain: in bit_vector(3 downto 0);
		bin: in bit_vector(3 downto 0);
		start: in bit;
		reg2_out: out bit_vector(3 downto 0));
	end component;
	
	for all: prob21 use entity work.prob21;
  
  begin
    prob21a: prob21
			port map (misccontrol => op_t, status => status_t, clk => clk_t, 
								ain => ain_t, bin => bin_t, start => start_t, reg2_out => reg2_t);

    process
			variable vline: line;
			variable v1: bit_vector(3 downto 0);
			variable v2: bit_vector(3 downto 0);
			variable v3: bit;
			file invect: text is "input5.txt";
    begin
			play <= '0', '1' after 50 ns;
			wait on play until play = '1';
			while not (endfile(invect)) loop
			  start_t <= '1';
				readline(invect, vline);
				read(vline, v1);
				read(vline, v2);
				read(vline, v3);
				ain_t <= v1;
				bin_t <= v2;
				op_t <= v3;
				wait until (status_t = '1');
			end loop;
    end process;
end behav;